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DMA Control Registers 5–0 (DCR[5–0])
Table 4-10. Address Attribute Registers (AAR[0–3]) Bit Definitions
Bit
Number
1–0
Bit Name
BAT[1–0]
Reset
Value
0
Bus Access Type
Description
Read/write bits that define the type of external memory (DRAM or SRAM) to access for the
area defined by the BAC[11–0],BYEN, BXEN, and BPEN bits. The encoding of BAT[1–0] is:
00 = Reserved
01 = SRAM access
10 = DRAM access
11 = Reserved
When the external access type is defined as a DRAM access (BAT[1–0] = 10), AA/RAS acts
as a Row Address Strobe (RAS) signal. Otherwise, it acts as an Address Attribute signal.
External accesses to the default area always execute as if BAT[1–0] = 01 (that is, SRAM
access). If Port A is used for external accesses, the BAT bits in the AAR3–0 registers must
be initialized to the SRAM access type (that is, BAT = 01) or to the DRAM access type (that
is BAT = 10). To ensure proper operation of Port A, this initialization must occur even for an
AAR register that is not used during any Port A access.
Note:
At reset, the BAT bits are initialized to 00.
4.7 DMA Control Registers 5–0 (DCR[5–0])
The DMA Control Registers (DCR[5–0]) are read/write registers that control the DMA operation
for each of their respective channels. All DCR bits are cleared during processor reset.
23
DE
11
DRS0
22
DIE
10
D3D
21
DTM2
9
DAM5
20
DTM1
8
DAM4
19
DTM0
7
DAM3
18
DPR1
6
DAM2
17
DPR0
5
DAM1
16
DCON
4
DAM0
15
DRS4
3
DDS1
14
DRS3
2
DDS0
13
DRS2
1
DSS1
12
DRS1
0
DSS0
Figure 4-9. DMA Control Register (DCR)
Table 4-11. DMA Control Register (DCR) Bit Definitions
Bit
Number
23
Bit Name
DE
Reset
Value
0
DMA Channel Enable
Description
Enables the channel operation. Setting DE either triggers a single block DMA transfer in the
DMA transfer mode that uses DE as a trigger or enables a single-block, single-line, or
single-word DMA transfer in the transfer modes that use a requesting device as a trigger. DE
is cleared by the end of DMA transfer in some of the transfer modes defined by the DTM bits.
If software explicitly clears DE during a DMA operation, the channel operation stops only
after the current DMA transfer completes (that is, the current word is stored into the
destination).
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
4-27
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